In recent years, a communication system, such as DSRC (Dedicated Short Range Communication) which is designed for short ranges, which is used for road-to-vehicle communication in such as ETC (Electronic Toll Collection System), a commercial car management system and the like, is classified into the optical type and the radio-wave type. The communication system is generally deemed to be available for communications in a range of several meters to several hundred meters. The specifications of this system are established by ARIB STD (Association of Radio Industries Businesses standard)-T55 Standard and STD-T75 Standard, and employs a carrier frequency in a range of 5772.5 to 5847.5 MHz for a radio communication system.
A SMART PLATE (System of Multifunctional integration of Automobiles and Roads in Transport in 21st Century PLATE) system which has been progressively developed as part of this DSRC involves an IC chip on a current number plate which records information on the number plate and information described in a car registration file, and is now under investigation as an infrastructure related to individual car information indispensable for popularizing ITS (Intelligent Transport Systems), or as a means for identifying cars in car traffic administration.
This system is targeted to be capable of operating for five years without replacing a built-in battery by detecting a start signal to intermittently operate the system. A weak signal of −60 dBm in a 5.8 GHz band is used for the start signal, and a circuit is required to stably detect such a signal.
A diode-based detector circuit is known for detection of radio frequency signals, and FIG. 1A shows a representative circuit example thereof. 101 designates an RF input terminal; 102 designates an output terminal; 105 designates a power terminal; D1, D2 designate diodes; C11, C12 designate capacitors; and R11 designates a resistor. In this circuit, during half period A of an input RF signal shown in FIG. 1B, a current flows into input terminal 101 through diode D1, and capacitor C11 is charged. In the next half period B, no current flows because diode D1 is biased in the opposite direction. In this half period, a current flows from capacitor C11 through diode D2 to charge capacitor C12. Finally, the potential on capacitor C12 increases by a charge charged in each half period. This circuit performs rectification by taking advantage of a non-linear effect of the diodes to charge each capacitor only for one-half period, so that this rectifier circuit is called a “half-wave double voltage rectifier circuit.”
A start signal output circuit using such a half-wave double voltage rectifier circuit has been proposed (for example, see JP-2004-194301-A (referred to as Patent Document 1 hereinafter)). FIG. 2 is a circuit diagram of the start signal output circuit which is disclosed in Patent Document 1. This circuit generally comprises detector/amplifier circuit 210, determination circuit 220 for amplifying and binarizing a detected start signal, and binarization circuit 230, and detects and amplifies an RF signal applied from RF input terminal 101 to generate a determination output from output terminal 102.
In detector/amplifier circuit 210, a half-wave double voltage rectifier circuit comprises capacitor C21 which additionally operates for input matching; smoothing capacitor C22; and diode-connected transistors Q3, Q4, where capacitors C21, C22 and transistors Q3, Q4 correspond to capacitors C11, C12 and diodes D2, D1 in FIG. 1A. Transistors Q7, Q8 comprises a current mirror circuit, where a current of reference transistor Q7 in the current mirror circuit is determined by the resistance value of resistor R21 which is a load resistance. A differential amplifier circuit is comprised of bipolar transistors Q1, Q2 which are loaded with a MOS transistor, and its total current is made constant by the current mirror circuit. While diode-connected transistors Q5, Q6 and capacitor C23 are connected to transistor Q2 as well, symmetrically to those of transistor Q1, the signal from RF input terminal 101 is not applied to this side. Therefore, transistor Q2 is applied with a constant bias at all times as a reference signal. A base current of transistor Q1 of the differential amplifier is supplied from transistor Q3 of the half-wave double voltage rectifier circuit, and the output of the differential amplifier is supplied to determination circuit 220.
In detector/amplifier circuit 210, when no RF signal is applied, the half-wave double voltage rectifier circuit comprised of transistors Q3, Q4 and capacitors C21, C22 is identical in configuration to a bias circuit comprised of transistors Q5, Q6 and capacitor C23 for applying the reference potential of the differential amplifier. Therefore, in the case where in-plane variations of elements within a chip can be neglected, two input terminals of the differential amplifier can be applied with the same potential at all times even if the element characteristics generally fluctuate due to fluctuations in processes or even if an ambient temperature varies. Accordingly, this circuit can correctly detect even a very small signal amplitude.
In addition, a rectifier circuit having diodes connected in series at multiple stages is also known (see, for example, John F. Dickson, “On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique”, IEEE Journal of Solid-State Circuits, vol. SC-11, No. 3, pp. 374-378, 1976 (referred to as Non-Patent Document 1 hereinafter)). FIG. 3 is a circuit diagram of the multi-stage connected rectifier circuit proposed in Non-Patent Document 1 (although the shown example is a six-stage connected circuit, the actual number of stages is larger than this). In FIG. 3, 102 designates an output terminal; 103 designates a DC bias terminal; 106, 107 designate clock input terminals which are applied with clocks at opposite phases to each other; D designates a diode; and C designates a capacitor. According to this circuit, a voltage increase is provided for each stage of the diode, the voltage increase being obtained by subtracting a ripple voltage due to charging and discharging of the capacitor associated with an output current and a forward voltage of the diode from an amplitude based on a clock at a diode node. In the circuit shown in FIG. 3, the diode can be replaced with a diode-connected MOS transistor. In this event, the diode forward voltage used in calculating the aforementioned voltage increase is replaced with the threshold voltage of the MOS transistor.